The posting
We are seeking result-driven candidates who can excel in a fast-pace work environment and possess a strong desire to make a meaningful impact within the organization. You will be part of the Custom Layout engineering team in undertaking physical design implementation of Foundation IP, Analog IP and RFIC for next-generation process platform developments.
Job Responsibilities:
- Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including IO/ESD Foundation IP, Analog IP and RFIC, across multiple process nodes and diversified foundries.
- Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning layout construction, physical verification and QA flow sign-off.
- Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project.
- Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area.
Requirements:
- Bachelor’s degree in Electrical/Electronic Engineering.
- Minimum of 3 years of direct experience in custom Foundation IP (IO/ESD) and/or RF/Analog layout implementation. Hands-on experience in advanced CMOS technologies (FinFETs/GAA) in a critical factor.
- Proficient in technical knowledges related to: Foundry DRM of advanced CMOS technologies, design for manufacturability (DFM), floorplanning techniques for hierarchical layout designs, SI/PI, EM/IR and ESD backend implementation flows.
- Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing, matching and top-down integration flow.
- Proficient in Cadence/Synopsys layout editor and physical verification tools; analytical and skillful in debugging physical verification such as DRC/LVS/ERC/ANT/PERC and all other verifications.
- Effective cross-team communication and time management skills.
- Proficient in IO/ESD layout and familiar with the layout requirement is a plus.
Interestedcandidates may apply through the application system. We regret that onlyshortlisted candidates will be notified.
PERSOL Singapore PteLtd • UEN No. 200007268E • EA License No. 01C4394 • EA Registration No.R22111378 (Ong Xin Yee)
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