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Open nowPosted 20 days ago

Process Engineer - Poly Etch

MyCareersFuture94,028 open roles

Pay
SGD 4,400 – SGD 8,800 a month
Where
Central, Singapore
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Your applicationOpen nowProcess Engineer - Poly EtchMyCareersFuture · Central, Singapore

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  2. 3.3%3 days
  3. 7.7%7 days
  4. 14.0%14 days
  5. 33.7%30 days
This job: posted 20 days ago

The posting

YOUR ROLE

  • Manage a cost-effective wafer fabrication process by providing engineering support to the production line to achieve the organization’s targeted manufacturing performance. Take full ownership of all engineering issues for the assigned process.
  • Maintain and support day-to-day manufacturing activities through real-time problem analysis and timely implementation of effective solutions.
  • Ensure smooth process flow with high quality, high yield, and low cost by working closely with Maintenance Specialists, Production Supervisors, and Shift Engineers to achieve committed targets.
  • Provide cross-functional, cross-department, and cross-fab support based on operational needs and priorities.
  • Train new engineers and share technical knowledge to support team development.
  • Support shift operations as needed and return to normal shift assignment for process/project work when assigned.
  • Take responsibility for trench etch processes within the poly team.

YOUR SKILLS & EXPERIENCES

  • Bachelor’s degree in Electrical/Electronics Engineering, Mechanical Engineering, Materials Engineering, Chemical Engineering or a related discipline.
  • Around 2 years of experience with etch processes
  • Experience in profile control and process stability.
  • Ability to conduct real-time problem analysis for SPC OOC/OOS, defect failures, and FDC failures, and determine appropriate solutions by working with all relevant stakeholders.
  • Ensure all basic inline investigations are reported in real time to the relevant owners with complete and accurate details.
  • Ability to set up process recipes for newly introduced processes.
  • Ability to establish a robust process control system to maintain the lowest possible Wafer at Risk (WAR) level, maximize the signal-to-noise ratio for SPC and FDC, and minimize human dependency.
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