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Open nowPosted 27 days ago

Researchers (Secure FPGA Design and Verification)

MyCareersFuture94,028 open roles

Pay
SGD 6,300 – SGD 8,200 a month
Where
West, Singapore
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Your applicationOpen nowResearchers (Secure FPGA Design and Verification)MyCareersFuture · West, Singapore

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This job: posted 27 days ago

The posting

About TUMCREATE

TUMCREATE is a multidisciplinary research platform of the Technical University Munich (TUM) at the Singapore Campus for Research Excellence and Technological Enterprise (CREATE). We are joining forces with universities, public agencies, and industry for the advancement of future technologies.

Our research program on post-quantum Security, ‘QUASAR - QUANTUM SECURITY AND RESILIENCE FOR EMERGING TECHNOLOGIES’ funded by Singapore’s National Research Foundation (NRF), is a collaborative effort between the Technical University Munich (TUM), Fraunhofer Singapore, Nanyang Technological University (NTU), the National University of Singapore(NUS). At TUMCREATE, we will focus on developing an open and verifiable Quantum safe RISC-V processor platform as a foundation for the QUASAR program.

As part of the QUASAR team, you will work alongside renowned scientists in Integrated Circuit (IC) design, security, and quantum technologies.

Please visit www.tum-create.edu.sg for more information about TUMCREATE.

Job Title/Position

Research Fellow / Research Associate / Research Engineer (Secure FPGA Design and Verification)

Job Purpose/Objective of the Position:

We are seeking a Research Fellow (PhD holder) / Research Associate (PhD student with Master’s degree) / Research Engineer to join the QUASAR project, focusing on secure FPGA-based system development and verification using RISC-V platforms.

This role emphasizes RTL design, verification, and system bring-up, and is well-suited for fresh graduates interested in hardware verification, system integration, and open-source hardware platforms.

This is a fixed term contract until March 2029 when applicable.

Job Responsibilities:

FPGA System Bring-up& Validation

  • Support the deployment and bring-up of CVA6-based SoC systems on FPGA platforms (Genesys 2)
  • Debug system-level issues,including boot flow (bootloader, DRAM initialization, peripheral access) and interface connectivity (UART, SPI,Ethernet, JTAG)
  • Validate system functionality through bare-metal programs and OS-level workloads (e.g., Linux, RTOS)

Verification & Debug

  • Develop and maintain verification workflows for FPGA-based RISC-V systems: Simulation (e.g., Verilator-based flows) and FPGA-based validation
  • Perform function alverification and debugging of RISC-Vcore integration (CVA6), Memory subsystem, interconnect, and peripheral interfaces.
  • Analyze and debug issues across abstraction layers: RTL bugs, Integration mismatches, and timing/synthesis-related issues.

Hardware Security Verification and Analysis

  • Research, develop and design-time verification methodologies for hardware security features in RISC-V systems
  • Evaluate and improve side-channel resistance (e.g., timing, power, and micro architectural leakage) in the context of a post-quantum secure RISC-V processor platform

Tool Flow & Automation Support

  • Work with existing FPGA flows (e.g., Vivado-based flows used in CVA6 FPGA implementation)
  • Develop scripts(Python/TCL) for building automation, regression testing, and results analysis.
  • Support integration with open-source simulation and verification tools

Job Requirements/Competencies:

  • Degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields
  • Strong foundation in digital design (RTL, timing, pipelining)
  • Hands-on experience with FPGA design flows
  • Familiarity with RISC-Varchitecture or SoC design
  • Programming skills in C/C++ and/or Python
  • Exposure to hardware verification methodologies (simulation, testbench design)
  • Familiarity with: Linux-based embedded systems and Debug tools (e.g., JTAG, GDB)
  • Interest in system-level debugging and cross-layer analysis

What TUM CREATE offers you:

  • Hands-on experience with a state-of-the-art open-source RISC-V coreon FPGA
  • A well-established FPGA platform with a clearly defined research scope
  • Close supervision within an international, interdisciplinary research project
  • A collaborative and inclusive world-class research environment
  • Competitive salary that is commensurate with experience
  • Medical insurance
  • Good amount of leave/vacation days
  • Vibrant, modern and positive working environment in Singapore
  • Campus-sited office location with a host of facilities
  • In-building perks including gym, game room and coffee room

Applications

Please send the following compulsory documents

  • cover letter
  • CV
  • university transcripts

to [email protected].

Only shortlisted candidates will be contacted.

We look forward to your application!

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