The posting
About the Role
We are looking for a Digital Implementation / STA Engineer to support ASIC development activities covering logic synthesis, formal verification, timing analysis and timing closure. The successful candidate will work closely with front-end and back-end design teams to ensure robust timing constraints, efficient implementation flows and successful full-chip timing closure.
Key Skills
- ASIC / Digital IC Design
- Logic Synthesis
- Static Timing Analysis (STA)
- Timing Closure
- SDC
- Timing ECO
- Formal Verification
- Verilog
- Synopsys Design Compiler (DC)
- Formality
- PrimeTime (PT)
- Tcl / Perl / Python
- DFT / BIST / SCAN / JTAG / ATPG
Key Responsibilities
- Logic Synthesis, Formal Verification & STAResponsible for the development, maintenance and quality control of flows related to logic synthesis, formal verification and Static Timing Analysis (STA).Ensure the robustness, accuracy and efficiency of relevant implementation flows.
- Timing Constraint DevelopmentWork closely with the front-end design team to develop and review module-level timing constraints.Collaborate with the front-end team to develop and perform quality checks on full-chip flattened SDC (Synopsys Design Constraints).
- Full-Chip Timing Analysis & ClosureExecute full-chip STA and perform timing analysis.Responsible for full-chip timing ECOs and support overall timing closure.Work closely with front-end and back-end design teams to identify and resolve timing-related issues.
Job Requirements
- Education & BackgroundBachelor’s degree or above in Electronic Information Engineering, Microelectronics, Integrated Circuit Engineering, Artificial Intelligence, or a related discipline.
- Logic Synthesis & Formal VerificationStrong proficiency in Verilog.Solid understanding of logic synthesis flows, methodologies and full-chip synthesis strategies.Experience in formal verification debugging is preferred.
- STA & Timing ClosureStrong proficiency in SDC.Good understanding of full-chip Static Timing Analysis (STA) and timing closure methodologies.Experience with timing analysis and timing ECO implementation is preferred.
- EDA Tools & ScriptingHands-on experience with commonly used EDA tools for logic synthesis, formal verification and static timing analysis.Proficiency in Tcl, Perl and Python scripting.Strong scripting and flow automation capabilities will be an advantage.
- DFT KnowledgeFamiliarity with Design for Test (DFT) concepts is preferred.Knowledge of common DFT methodologies, including BIST, SCAN, JTAG and ATPG, will be an advantage.
- Professional CompetenciesSelf-motivated, proactive and capable of working independently.Strong analytical and problem-solving skills.Good communication and teamwork skills.Demonstrates a strong sense of ownership and commitment to delivering high-quality results.
