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Open nowPosted 9 days ago

Senior/ IC Design Engineer (Design Verification)

MyCareersFuture94,028 open roles

Pay
SGD 5,000 – SGD 10,000 a month
Where
Singapore
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Your applicationOpen nowSenior/ IC Design Engineer (Design Verification)MyCareersFuture · Singapore

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The clock on this job

Early applications get read.

7.7% of postings close within 7 days. Measured by our own scanner across the market.

Share of postings closed within
  1. 1.6%1 day
  2. 3.3%3 days
  3. 7.7%7 days
  4. 14.0%14 days
  5. 33.7%30 days
This job: posted 9 days ago

The posting

Job Description

  • Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications.
  • Build and maintain SystemVerilog/ UVM-based verification environments and testbenches
  • Develop directed and constrained-random tests, assertions(SVA), and functional coverage.
  • Debug DUT issues, analyze simulation results, and drive verification closure.
  • Collaborate with cross-functional teams throughout the design and verification lifecycle.
  • Support regression automation and continuously improve verification methodologies.
  • Leverage AI-assisted tools and data-driven techniques to enhance verification efficiency, coverage, and debug productivity.

Requirements

  • Bachelor's or Master's degree in Electrical, Electronic, Computer Engineering or related field with at least 1 year of experience.
  • Hands-on experience in ASIC/SoC/IP verification using SystemVerilog and UVM.
  • Knowledge of constrained-random verification, assertions (SVA), functional coverage, and scripting languages such as Python/ Perl/ Tcl.
  • Experience with industry-standard EDA tools (e.g., Cadence or Synopsys).
  • Familiarity with AI/ML-assisted EDA tools or the use of generative AI to improve verification workflows is an advantage.
  • Strong analytical, problem-solving, and communication skills.

We invite qualified candidates to apply online or submit a detailed resume to [email protected]

.

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