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Open nowPosted 6 days ago

Senior Packaging Engineer (Advanced Semiconductor Packaging)

MyCareersFuture94,028 open roles

Pay
SGD 6,000 – SGD 9,000 a month
Where
West, Singapore
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Your applicationOpen nowSenior Packaging Engineer (Advanced Semiconductor Packaging)MyCareersFuture · West, Singapore

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The clock on this job

Early applications get read.

7.7% of postings close within 7 days. Measured by our own scanner across the market.

Share of postings closed within
  1. 1.6%1 day
  2. 3.3%3 days
  3. 7.7%7 days
  4. 14.0%14 days
  5. 33.7%30 days
This job: posted 6 days ago

The posting

Key Responsibilities

· Package Architecture & Design: Define and develop semiconductor package solutions (e.g., Flip-Chip, Wirebond, 2.5D/3D, Chiplets, CoWoS, FOWLP, SiP) from concept to mass production.

· Evaluate package architectures, interconnect strategies, substrate stack-ups, and material selections to meet electrical, thermal, mechanical, and reliability requirements.

· Design and define substrate stack-ups, routing strategies, and interconnect structures to meet high-speed, high-density, and manufacturability requirements.

· Collaborate with SI/PI teams to optimize package-level electrical performance including high-speed IO and power delivery.

· Simulation & Multi-Physics Collaboration: Collaborate with thermal and mechanical engineering teams to perform simulations (warpage, stress, CTE mismatch).

· New Product Introduction (NPI) &Manufacturing: Lead package development through NPI to high-volume manufacturing (HVM), ensuring DFM, cost, yield, and reliability targets.

· Collaborate with OSAT vendors and substrate suppliers to ensure process readiness, qualification, and ramp.

· Process Development & Yield Improvement: Develop backend processes (bumping, assembly, molding, underfill).

· Materials & Reliability Engineering: Evaluate packaging materials and define BOM.

· Ensure reliability through qualification and failure analysis.

· Cross-functional Collaboration: Work with IC design, SI/PI, system, and manufacturing teams for chip-package-system co-design.

Requirements: · Master’s degree or above in Mechanical Engineering, Electrical Engineering, Materials Science, Microelectronics, or related fields.

· 3+ years of experience in semiconductor packaging, preferably in advanced packaging.

· Strong understanding of packaging technologies such as Flip-Chip, FOWLP, WLCSP, and 2.5D/3D integration.

· Hands-on experience in substrate design (stack-up definition, routing, and manufacturability).

· Experience with NPI, OSAT engagement, and high-volume manufacturing.

· Knowledge of package materials, assembly processes, and reliability standards.

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