The posting
Key Responsibilities Key Responsibilities
RTL Design and Verification
- Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring, and diagnostic IP targeting analog and mixed-signal failure detection.
- Design and verify digital logic blocks such as test controllers, sequencing logic, sensor/interface control logic, measurement and monitoring logic, data capture and comparison logic, and failure detection and reporting logic.
- Build clean register and bus-connected interfaces, for example APB, AHB, or AXI-lite based control and status paths, to enable firmware interaction and subsystem integration.
- Develop testbenches, assertions, checkers, and block or subsystem-level verification environments to validate controller behavior, detection logic, configuration programming, fault response, and status reporting.
- Plan and execute functional verification for normal, corner, negative, and fault-injection scenarios, with adequate coverage of critical diagnostic behaviors.
- Collaborate with analog and mixed-signal designers to create or use behavioral models, stubs, and interface abstractions for realistic verification of failure mechanisms and observability paths.
- Debug RTL and simulation issues through waveform analysis, assertion-based checks, root-cause investigation, and close interaction with integration and product teams.
- Ensure the RTL is modular, reusable, timing-aware, synthesis-friendly, and scalable for integration across multiple SoC derivatives.
SoC Integration
- Integrate custom DFT / diagnostic IP into SoC subsystems and system-level test architecture with proper consideration for clock/reset structure, interrupt handling, and status visibility.
- Work closely with SoC integration and DFT teams to ensure compatibility with system test infrastructure, production test flows, diagnostic mechanisms, and firmware control requirements.
- Support integration readiness by addressing CDC, reset interactions, timing considerations, low-power implications, and implementation handoff requirements.
Cross-Functional Collaboration
- Work closely with digital, analog, and mixed-signal design teams, DFT engineers, SoC architects, and product/test engineering teams throughout the design and validation cycle.
- Translate analog or mixed-signal failure modes into robust digital detection logic suitable for on-chip test, screening, and diagnosis.
- Contribute to technical discussions on architecture tradeoffs, observability strategy, and practical silicon debug readiness.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, with 5–7 years of relevant experience.
- Strong hands-on experience in RTL design using Verilog/SystemVerilog.
- Practical experience in RTL verification, simulation, and debugging methodologies.
- Solid understanding of ASIC / SoC design flow including coding, simulation, synthesis, and integration.
- Good foundation in digital design concepts such as FSM design, datapath design, bus protocols (AXI/AHB/APB), clock-domain handling, reset strategy, and timing considerations.
- Experience working in complex SoC environments with cross-functional teams.
Preferred Qualifications
- Experience developing control, monitoring, or diagnostic IP associated with analog or mixed-signal subsystems.
- Exposure to behavioral modeling or interface definition for analog and mixed-signal verification use cases.
- Familiarity with subsystem-level integration, production screening considerations, and silicon debug support.
- Working knowledge of scripting or automation for verification, regression, or design productivity is an advantage.
