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Open nowPosted yesterday

PDK Engineer

nxp803 open roles

Where
Nijmegen
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Your applicationOpen nowPDK Engineernxp · Nijmegen

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The clock on this job

Early applications get read.

13.9% of postings close within 7 days. Measured by our own scanner across the market. nxp postings stay open a median of 19 days.

Share of postings closed within
  1. 2.2%1 day
  2. 4.7%3 days
  3. 13.9%7 days
  4. 22.4%14 days
  5. 38.1%30 days
  6. 59.0%60 days
This job: posted yesterday

nxp median: 19 days open

The posting

Join the PDK team in Nijmegen and help deliver reliable design environments for advanced semiconductor and packaging technologies.

Our team integrates foundry-provided Process Design Kits into a standardized NXP environment. We work with foundries, EDA vendors, technology experts, packaging teams, and IC designers to ensure that PDKs meet NXP’s quality, reliability, and usability requirements.

Your Responsibilities

  • Develop, integrate, and maintain physical-verification rule decks and runsets for bulk CMOS, FinFET, SOI and FD-SOI, RF CMOS, BiCMOS, BCD, and high-voltage technologies.
  • Develop and support DRC, LVS, ERC, reliability-verification, metal-fill, and density-verification flows, including Calibre PERC where applicable
  • Develop and maintain layout parasitic extraction technology files and LPE/PEX flows.
  • Develop and integrate technology and reliability data for electromigration and voltage-drop analysis, supporting EM/IR verification flows.
  • Integrate and qualify foundry-provided rule decks, technology files, extraction data, and device models.
  • Automate PDK testing, regression, and validation.
  • Investigate technical issues and work with foundries and EDA vendors to resolve them.
  • Support design teams during PDK adoption, verification, and tape-out.
  • Evaluate new EDA tools, methodologies, and design-flow capabilities.

What You Bring

  • At least eight years of relevant experience in physical verification, parasitic extraction, EM/IR verification, or PDK development.
  • Hands-on experience developing physical-verification rule decks using at least one of the following platforms: Siemens Calibre using SVRF or TVF Cadence Pegasus, PVS, or Assura Synopsys IC Validator
  • Strong knowledge of DRC, LVS, parasitic extraction, and semiconductor sign-off methodologies.
  • Experience with relevant EDA tools, such as:Siemens Calibre nmDRC, nmLVS, PERC, or xRC Cadence Pegasus, Quantus, or Voltus Synopsys IC Validator, StarRC, or RedHawk-SC
  • Experience working in Linux or UNIX-based EDA environments.
  • Proficiency in at least two relevant programming or scripting languages, such as Python, Tcl, shell scripting, Perl, Cadence SKILL, C, or C++.
  • Strong analytical, debugging, communication, and collaboration skills.

Preferred Qualifications

  • A Master of Science (MSc) or PhD in Electrical Engineering, Microelectronics, Semiconductor Technology, Applied Physics, Computer Engineering, or a related discipline.
  • Candidates with a bachelor’s degree and substantial relevant industry experience are also encouraged to apply.
  • Experience with PDK regression automation and quality assurance.
  • Knowledge of machine learning or generative AI for engineering automation, data analysis, knowledge retrieval, or verification debugging.

Your Impact

You will help provide NXP design teams with consistent, high-quality PDKs for advanced semiconductor technologies. Your work will improve design productivity, sign-off quality, and the integration of silicon and packaging technologies.

More information about NXP in the Netherlands...

#LI-f5d0

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