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Principal DfT Engineer

nxp803 open roles

Where
Bangalore
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Your applicationOpen nowPrincipal DfT Engineernxp · Bangalore

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The clock on this job

Early applications get read.

13.9% of postings close within 7 days. Measured by our own scanner across the market. nxp postings stay open a median of 19 days.

Share of postings closed within
  1. 2.2%1 day
  2. 4.7%3 days
  3. 13.9%7 days
  4. 22.4%14 days
  5. 38.1%30 days
  6. 59.0%60 days
This job: posted today

nxp median: 19 days open

The posting

Job Title: Design for Test (DfT) Principal Engineer – G4

Location: Bangalore

Role Summary

The Principal DfT Engineer is a senior technical expert responsible for the development, implementation and verification of advanced Design-for-Test solutions for complex SoCs and IPs. The role provides deep expertise across digital and Analog/Mixed-Signal (AMS) DfT, translating the DfT architecture and product requirements into robust, reusable and production-ready implementations.

The Principal DfT Engineer solves complex DfT challenges, drives methodology and automation improvements, supports silicon bring-up and diagnosis, and provides technical guidance and mentoring to other DfT engineers. The role works closely with DfT Architects, System Architects, digital and analog designers, Verification, Synthesis team, Physical Design, Product Engineering and Test Engineering.

Key Responsibilities

Advanced DfT Implementation

• Translate the DfT architecture and product requirements into detailed, implementable DfT solutions.

• Develop and implement scan, ATPG, test compression, MBIST, JTAG/IJTAG, boundary scan, and OCC solutions.

• Perform DfT insertion, verification, design-rule analysis, coverage analysis and optimization.

• Ensure that implemented solutions meet the agreed requirements for quality, coverage, test time, cost and schedule.

Analog/Mixed-Signal DfT

• Develop and implement DfT solutions for analog and mixed-signal IP and SoC functions.

• Work closely with analog designers and Product/Test Engineering to improve controllability, observability and diagnosability of analog functions.

• Develop test solutions for functions such as PLLs, ADCs/DACs, PHYs, sensors, analog front ends and high-speed interfaces.

• Develop and apply Analog BIST, Mixed-Signal BIST, loopback and on-chip measurement or monitoring techniques where appropriate.

• Optimize the balance between structural test, functional test, embedded test and ATE-based test.

• Support analog and mixed-signal characterization, diagnosis and test-cost reduction.

Verification & Silicon

• Drive DfT verification at RTL and gate level, including gate-level simulation.

• Generate, validate and optimize ATPG and iJTAG test patterns.

• Support pattern bring-up and debug on automated test equipment (ATE).

• Analyze silicon failures and support root-cause analysis and diagnosis.

• Improve test coverage, test time, diagnosis capability, manufacturing test efficiency and product quality.

• Support silicon bring-up, characterization and production ramp.

Methodology & Innovation

• Develop and deploy new DfT methodologies, flows and automation.

• Evaluate and introduce new digital and AMS DfT techniques where they improve quality, efficiency, coverage or test cost.

• Drive reuse and standardization of proven DfT solutions across projects.

• Contribute technical expertise to internal DfT methodology and innovation initiatives.

• Collaborate with EDA vendors on tool capabilities, issue resolution and flow improvements.

Technical Leadership & Competence Development

• Act as a technical reference and problem solver for complex digital and AMS DfT issues.

• Perform technical reviews and ensure implementation and verification quality.

• Coach and mentor DfT engineers and contribute to their technical development.

• Share expertise, lessons learned and best practices across projects and sites.

• Contribute to hiring, technical assessments and competence development.

• Collaborate effectively with DfT Architects while maintaining a clear focus on technical realization, methodology and execution.

Expected Impact for a G4 Principal Engineer

A G4 Principal DfT Engineer is expected to provide recognized technical expertise beyond an individual work package and to make a sustained contribution across projects and the DfT competence.

Is consulted for complex DfT implementation, verification, AMS testability and silicon-debug challenges.

Technically leads difficult assignments and delivers solutions for problems that may be ambiguous or not previously encountered.

Drives measurable improvements in DfT quality, coverage, efficiency, reuse, automation and test cost.

Introduces and industrializes advanced digital and AMS DfT solutions.

Raises the technical capability of the wider DfT team through mentoring, reviews and knowledge sharing.

Influences technical choices through expertise and evidence, while the DfT Architect retains ownership of the overall DfT strategy and architecture.

Qualifications

Education

• MSc or PhD in Electrical Engineering, Computer Engineering or a related discipline.

Experience

• Typically 12+ years of experience in semiconductor development, with substantial hands-on DfT experience.

• Proven experience as a senior DfT engineer, lead engineer or technical lead.

• Track record of delivering complex SoC or IP DfT solutions from implementation through production.

• Practical experience with silicon bring-up, diagnosis and manufacturing-test collaboration.

• Experience with Analog/Mixed-Signal DfT implementation or test development.

Technical Expertise

Strong knowledge of:

• Scan implementation and ATPG

• Test compression and coverage optimization

• IJTAG / IEEE 1687

• JTAG / IEEE 1149.x and boundary scan

• Memory BIST and repair

• Logic BIST

• On-chip clock control concepts

• Analog DfT and mixed-signal test

• Analog and Mixed-Signal BIST, loopback and embedded measurement techniques

• Fault modelling, coverage analysis and diagnosis

• Silicon debug and characterization

• Production test and ATE pattern bring-up

• RTL design and gate-level STA simulation

• Automotive quality requirements and production-readiness practices

• Modern EDA tools from Siemens EDA, Synopsys and Cadence

Leadership Competencies

• Deep technical problem solving

• Technical leadership and influencing

• Cross-functional collaboration

• Coaching and mentoring

• Continuous improvement and innovation

• Ownership and delivery focus

• Clear and effective communication

More information about NXP in India...

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