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Open nowFirst seen 3 days ago

Design Verification Engineer

Omnicom Production7 open roles

Where
Toponas, Colorado, United States, Remote
Work mode
Remote
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Your applicationOpen nowDesign Verification EngineerOmnicom Production · Toponas, Colorado, United States, Remote

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The clock on this job

Early applications get read.

12.1% of postings close within 7 days. Measured by our own scanner across the market.

Share of postings closed within
  1. 2.1%1 day
  2. 4.5%3 days
  3. 12.1%7 days
  4. 19.1%14 days
  5. 35.6%30 days
  6. 52.7%60 days
This job: first seen 3 days ago

The posting

Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits?

Omnicom Production is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients worldwide. Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM based peripherals, and mixed signal DSPs. Successful candidates for this role will support verification of advanced CPU/GPU based SOCs.

Whether you are an experienced veteran looking for new challenges, or a talented engineer seeking to broaden your experience, we can offer exciting options for your career.

RESPONSIBILITIES:

  • Verify complex design blocks using equally complex SV/UVM verification environments
  • Develop and execute pre-silicon verification test plans
  • Develop directed and random verification tests to validate block and IP functionality
  • Develop verification components and tools
  • Develop verification functional coverage using industry standard coverage analysis tools/methods
  • Debug regression fails
  • Replicate functional issues found in external environments or post-silicon; review/enhance tests to verify bug fixes

REQUIRED SKILLS AND EXPERIENCE:

  • 3 or more years of proven verification experience in a hardware development setting
  • Strong background in System Verilog and UVM verification methodologies
  • Strong debug skills and experience with debug tools such as DVE/Verdi
  • Proficiency in Object Oriented programming, computer architecture and data structures
  • Strong analytical/problem solving skills and pronounced attention to details
  • Strong interpersonal and communication skills
  • Must be comfortable working across geographies

DESIRED SKILLS:

  • Experience architecting/developing verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar
  • Experience in other related domains such as formal verification, RTL design, or software development

EDUCATION: Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer Science

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