The posting
𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀
𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟭𝟮𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟮𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟭𝟮-𝟮𝟬 𝗟𝗣𝗔)
Experience: 3+ yrs
Location: Remote (India), India
Job Type: Full-time
We are looking for an experienced ASIC / FPGA Design Engineer with strong hands-on expertise in digital design, RTL development, verification, and implementation flows. The ideal candidate will have practical experience taking chip designs from specifications and RTL through verification, synthesis, physical design, and timing closure.
This role combines semiconductor engineering expertise with the development of technical evaluations for AI systems. You will create realistic engineering tasks, develop reference solutions, assess AI-generated designs, and identify functional, timing, and power-performance-area (PPA) issues. The focus is on applying real-world engineering judgement to evaluate how effectively AI agents perform complex chip-design tasks.
Requirements
Key Responsibilities
- Develop realistic engineering evaluation tasks covering RTL design, functional verification, synthesis, physical design, and sign-off.
- Write reference implementations in Verilog, SystemVerilog, or VHDL, supported by testbenches, constraints, and expected results.
- Define clear grading criteria and validation methods that reflect industry-standard engineering expectations.
- Review AI-generated RTL, testbenches, hardware designs, and implementation results to identify functional errors and design weaknesses.
- Diagnose verification failures, coverage gaps, timing violations, and suboptimal power, performance, and area decisions.
- Evaluate designs against functional correctness, timing constraints, resource utilisation, and implementation quality.
- Configure and maintain EDA-based environments that enable AI agents to execute realistic chip-design workflows.
- Work with tools from Synopsys, Cadence, Siemens, AMD/Xilinx Vivado, or Intel Quartus, as relevant to the evaluation.
- Develop tasks that assess synthesis quality, place-and-route results, static timing analysis, and timing closure.
- Identify recurring AI-agent failure patterns and convert them into new evaluation scenarios and more challenging engineering tasks.
- Collaborate with engineering and research teams to improve evaluation environments, testing methods, and technical benchmarks.
- Automate design flows, testing, and result analysis using scripting languages where appropriate.
- Document reference solutions, design assumptions, failure cases, and evaluation methodologies.
What Makes You a Great Fit
- 3–5 years of hands-on ASIC or FPGA design experience, preferably across multiple stages of the digital design flow.
- B.E./B.Tech or M.Tech in Electrical Engineering, Electronics Engineering, VLSI, or a related discipline.
- Strong RTL development skills in Verilog, SystemVerilog, or VHDL.
- Practical experience with design verification, including testbench development, debugging, coverage analysis, and UVM or similar methodologies.
- Working knowledge of EDA tools and workflows from Synopsys, Cadence, Siemens, AMD/Xilinx, or Intel.
- Understanding of logic synthesis, place-and-route, static timing analysis, timing constraints, and timing closure.
- Sound engineering judgement when evaluating power, performance, and area (PPA) trade-offs.
- Experience taking at least one project from specification through implementation or tape-out.
- Strong debugging, analytical, and problem-solving skills, with the ability to explain precisely why a design succeeds or fails.
- Familiarity with Python, Tcl, or Perl for design-flow automation is an advantage.
- Exposure to open-source tools such as Yosys, OpenROAD, Verilator, or cocotb is beneficial.
- Interest in AI engineering evaluations, reinforcement-learning environments, or model post-training is a plus, but not required.
