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Senior Software Engineer, GPU Systems

ByteDance1,422 open roles

Where
San Jose, California, United States of America
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Your applicationOpen nowSenior Software Engineer, GPU SystemsByteDance · San Jose, California, United States of America
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The clock on this job

Early applications get read.

8.1% of postings close within 7 days. Measured by our own scanner across the market. ByteDance postings stay open a median of 38 days.

Share of postings closed within
  1. 1.7%1 day
  2. 3.6%3 days
  3. 8.1%7 days
  4. 15.1%14 days
  5. 34.1%30 days
This job: first seen 4 hours ago

ByteDance median: 38 days open

The posting

About the Team We are a systems software team building the foundational software for large-scale GPU computing platforms. We work at the hardware/software boundary across the Linux kernel, accelerators, storage, firmware, and platform validation. We value rigorous engineering, clear interfaces, measurable performance and reliability, and upstream collaboration where appropriate. The team partners closely with hardware, architecture, product, validation, and production engineering groups to move new capabilities from design through dependable deployment.

About the Role You will build and optimize low-level software that makes modern GPU accelerators usable, observable, and reliable in production. Your work may span kernel drivers, runtime components, firmware interfaces, resource management, telemetry, debugging tools, and performance-critical paths. You will own technically difficult features end to end and collaborate across the stack while remaining primarily accountable for code, validation, and production outcomes.

Responsibilities - Design, implement, and maintain production GPU system software, including kernel-driver, runtime, firmware-interface, host-management components, debugging tracing and profiling tools, and GPU system performance measurement tools - Own accelerator features from proof of concept and architecture through implementation, pre-silicon or emulation validation, bring-up, qualification, and deployment. - Debug complex failures involving GPUs, CPUs, memory, PCIe or interconnects, IOMMU, firmware, operating systems, runtimes, and distributed workloads. - Profile workloads and remove bottlenecks in initialization, memory movement, scheduling, synchronization, communication, recovery, and device utilization. - Build automated tests, telemetry, dashboards, health checks, and diagnostic tools that make failures reproducible and regressions visible. - Partner with silicon, firmware, compiler, library, machine-learning framework, platform, validation, and production teams to deliver compatible system behavior. - Improve resilience through error detection, isolation, retry, reset, repair, graceful degradation, and clear operational procedures. - Review low-level designs and code, document hardware/software contracts, and share practical performance and debugging methods with peers.

Minimum Qualifications - Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent practical experience. - 3+ years of professional programming experience in C or C++ for low-level, embedded, kernel, driver, runtime, or performance-critical software. - Solid understanding of computer architecture, operating systems, concurrency, memory hierarchies, DMA, interrupts, and device I/O. - Hands-on experience with GPU or accelerator software in at least one layer, such as kernel drivers, runtimes, firmware, libraries, collective communication, or performance tooling. - Demonstrated ability to diagnose system failures using traces, logs, profilers, debuggers, counters, and controlled experiments. - Experience delivering and maintaining production-quality features across hardware and software teams.

Preferred Qualifications - Experience with CUDA, ROCm, Level Zero, OpenCL, Triton, CUTLASS, or comparable accelerator programming and runtime environments. - Knowledge of GPU scheduling, memory management, virtualization, PCIe, coherent interconnects, NUMA, or multi-GPU topology. - Experience with pre-silicon development, board bring-up, firmware communication, baseboard management controllers, or fleet qualification. - Familiarity with distributed training or inference and topology-aware communication libraries; this is preferred rather than a universal requirement.

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