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Open nowPosted 12 days ago

Senior AI System Architect

Credo40 open roles

Pay
$160,000 – $220,000 a year
Where
San Jose Office, United States
Work mode
On site
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Your applicationOpen nowSenior AI System ArchitectCredo · San Jose Office, United States

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The clock on this job

Early applications get read.

12.3% of postings close within 7 days. Measured by our own scanner across the market. Credo postings stay open a median of 1 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.5%3 days
  3. 12.3%7 days
  4. 19.3%14 days
  5. 35.6%30 days
  6. 57.8%60 days
This job: posted 12 days ago

Credo median: 1 days open

The posting

Job description

Team Credo is looking for a Senior AI System Architect to join our team in San Jose, CA, reporting to AVP, XPU system AI interface. This role needs to solve the system-level interconnection challenges that connect XPUs (NPU/GPU/custom silicon) into working AI infrastructure. This role needs to follow and define how compute elements are wired, networked, and orchestrated together at node, rack, and cluster scale so that large-scale LLM training and inference run efficiently across the platform. We strongly prefer candidates with a hands-on NPU hardware architect background and real experience taking NPU silicon into production deployment at scale.

Base salary range is $160,000 - $220,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

Why Credo

  • Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
  • People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
  • Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.

Qualifications

Basic Qualifications

  • Bachelor's degree in Computer Engineering, EE, CS, or related field required.
  • Three years in XPU or AI interconnect system architecture and micro architecture working experience.
  • Strong foundational understanding of computer architecture, including GPU, NPU, and/or CPU design principles.
  • Familiarity with large language model architectures and distributed training/inference concepts (e.g., parallelism strategies, model serving) through coursework, research, or personal projects.
  • Demonstrated analytical ability — for example, through published research, thesis work, or quantitative project work — with a track record of independently studying and synthesizing technical material.
  • Strong cross-functional leadership and communication skills, daily experience working with compiler, software, SOC & backend team preferred.

Preferred Qualifications

  • Master's or PhD in Computer Science, Artificial Intelligence, Engineering, or a related field.
  • Deep, hands-on NPU hardware architecture expertise.
  • Real, hands-on NPU architecture background, with direct experience participating in an NPU design from architecture definition through silicon bring-up, validation, and volume production deployment.
  • Working knowledge of high-speed interconnect or networking concepts (e.g., PCIe, Ethernet, RDMA) is a plus.

Responsibilities

  • Model the memory and interconnection architecture linking XPUs to memory and across node, rack, and cluster boundaries — not the internal design of the NPUs/GPUs/CPUs themselves.
  • Solve communication and topology bottlenecks that arise from all kinds of parallelism strategies during distributed LLM training and inference.
  • Define how XPUs utilize the memory and interconnect fabric, ensuring workloads map cleanly onto the network topology.
  • Work with silicon, memory, networking, and software teams to specify interconnect fabric requirements and resolve integration issues between compute nodes.
  • Bring hands-on NPU hardware architecture judgment to interconnect and system design decisions, informed by direct experience taking NPU silicon from definition through bring-up, validation, and production deployment.
  • Track leading open LLM architectures to anticipate how model structure will stress interconnect and system topology.

Job benefits

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.

Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, gender identity, sexual orientation, pregnancy, marital status, national origin, ethnicity, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [email protected].

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