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Open nowPosted today

IO Design Architecture Expert

IBM2,336 open roles

Where
Bangalore, IN
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Your applicationOpen nowIO Design Architecture ExpertIBM · Bangalore, IN

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The clock on this job

Early applications get read.

12.8% of postings close within 7 days. Measured by our own scanner across the market. IBM postings stay open a median of 15 days.

Share of postings closed within
  1. 2.2%1 day
  2. 4.5%3 days
  3. 12.8%7 days
  4. 20.6%14 days
  5. 35.6%30 days
  6. 58.4%60 days
This job: posted today

IBM median: 15 days open

The posting

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

We are seeking an experienced IO Design Architecture Expert to define, develop, and document chip‑level architecture for high‑performance IO bridges—such as PCIe bridges—within server‑class processor designs.

  • Architect and specify IO subsystem components, with a focus on PCIe and other server‑grade IO bridges.
  • Develop detailed architectural descriptions, interface definitions, and micro‑architecture guidance for implementation teams.
  • Collaborate with cross‑functional teams to ensure architectural integrity and compliance with industry standards.
  • 15-20 years of strong understanding of major IO and interconnect standards, including PCIe, PCI‑X, CXL, and related protocols.
  • Proficiency in:MSI and LSI interrupt mechanisms TCEs (Translation Control Entries) DMA ordering rules and transaction flows MMIO address mapping and access semantics Address Translation Services (ATS) and related coherency/translation features
  • Ability to translate architectural requirements into clear specifications used by design, verification, and firmware teams.
  • Proven experience in server‑class SoC or IO subsystem design is highly desirable.

• Specialized FPGA Knowledge: Experience with field-programmable gate array analysis and design, including use of design entry languages and design automation tools, is beneficial for driving innovation and efficiency in logic design.

• Advanced Static Timing: Deep understanding of static timing and its application in chip logic development can be advantageous in driving business results.

• Front-end Processing Expertise: Familiarity with front-end processing and its role in chip logic development can be valuable in shaping the future of cognitive systems logic design.

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