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Open nowPosted 59 days ago

芯片物理设计工程师

li/referral788 open roles

Where
Beijing, Chinese Mainland
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Your applicationOpen now芯片物理设计工程师li/referral · Beijing, Chinese Mainland

  1. YouYes, apply to this one.

  2. CV RocketCV written for this posting.

  3. 25 readersRecruiter, hiring manager, skeptic. Round after round.

  4. CV RocketApplied on li/referral's own form.

The reply lands in your private mailbox

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The clock on this job

Early applications get read.

12.3% of postings close within 7 days. Measured by our own scanner across the market. li/referral postings stay open a median of 1 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.5%3 days
  3. 12.3%7 days
  4. 19.3%14 days
  5. 35.6%30 days
  6. 57.8%60 days
This job: posted 59 days ago

li/referral median: 1 days open

The posting

1. 负责公司 芯片物理实现方向的总体技术路线规划，制定未来产品线的实现策略、方法学框架与技术标准。 2. 主导大规模 SoC / AI 加速器 / CPU / NPU 等核心芯片的 Floorplan、时钟树（CTS）、布局布线（P&R）架构设计与关键技术决策。 3. 负责复杂工艺节点（如 5nm/3nm/Chiplet/多电压域）的 PPA 优化策略制定、实现风险评估与技术攻坚，确保从 Netlist 到 GDSII 的全链路稳定性。 4. 牵引跨团队协作（架构、RTL、DV、DFT、工艺、封装、SI/PI），推动从设计到流片、量产的系统级收敛。 5. 主导物理实现方法学创新，包括 Timing ECO 策略、低功耗/多电压域优化、Congestion 管控、跨模块 Hierarchical 实现等体系建设。 6. 对外参与技术生态、工艺厂商合作、工具链深度优化，与 EDA 厂商共同探索新代工艺节点，实现行业领先的 PPA 指标。

1. 10–15 年以上 ASIC 物理设计经验，主导过 先进工艺节点（7nm/5nm/3nm） 的大型 SoC / AI 芯片成功量产项目。 2. 深入掌握 Floorplan、Placement、CTS、Routing、IRDrop、EM、SI/PI、MMMC、低功耗 UPF 等全流程技术。 3. 在 PPA 优化、时序收敛、Block/Top 多层级实现、Chiplet/3D IC 等方向具有专家级深度。 4. 熟悉 Synopsys、Cadence、Ansys 等主流 EDA 工具链，并具备驱动工具优化与影响工艺厂商技术路线的能力。 5. 能够从系统层面判断架构、RTL、验证、DFT 等对物理实现的影响，并给出可落地的反向约束建议。 6. 有带领大规模团队推进数十亿门级芯片流片的经验，能够进行组织级规划与技术决策。

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