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Open nowPosted 138 days ago

NoC设计工程师

li/referral788 open roles

Where
Shanghai, Chinese Mainland
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Your applicationOpen nowNoC设计工程师li/referral · Shanghai, Chinese Mainland

  1. YouYes, apply to this one.

  2. CV RocketCV written for this posting.

  3. 25 readersRecruiter, hiring manager, skeptic. Round after round.

  4. CV RocketApplied on li/referral's own form.

The reply lands in your private mailbox

3×more interviews than doing it yourself with ChatGPT.

The clock on this job

Early applications get read.

12.1% of postings close within 7 days. Measured by our own scanner across the market. li/referral postings stay open a median of 1 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.5%3 days
  3. 12.1%7 days
  4. 19.1%14 days
  5. 35.6%30 days
  6. 52.7%60 days
This job: posted 138 days ago

li/referral median: 1 days open

The posting

  • 负责SoC片上网络（NoC）的架构规划、微架构设计与RTL实现，包括接口单元、路由器、交换矩阵、仲裁器等核心模块。
  • 参与定义NoC拓扑结构、带宽需求及QoS策略，配合系统架构师完成性能建模与分析。
  • 使用Verilog/SystemVerilog完成高质量、可综合的RTL代码开发，编写配套的设计规格文档（High Level Description）。
  • 推动NoC设计的物理可实现性（PPA），与后端团队协作完成时序收敛、功耗优化及面积约束。
  • 负责或配合制定GALS（全局异步局部同步）跨时钟域设计方案，包括CDC处理、握手协议及异步FIFO设计。
  • 编写并维护Python脚本用于自动化设计流程，包括配置生成、覆盖率分析、性能数据处理等日常工程任务。
  • 配合验证团队定义验证计划，解决功能仿真中发现的设计缺陷。

学历与经验 - 电子工程、微电子、计算机工程或相关专业硕士及以上学历。 - 3～5年数字IC前端设计工作经验，具备完整的SoC设计或流片经历优先。 必备技能： - 精通Verilog / SystemVerilog硬件描述语言，能够独立编写符合工业标准的可综合RTL代码。 - 深入理解SoC互联协议与总线架构，包括但不限于AXI、ACE、CHI等。 - 熟悉计算机体系结构基础概念，包括Cache一致性、内存系统、主从设备访问模型等。 - 了解大型芯片物理实现流程，具备时序分析（STA）、功耗评估及与后端协作的经验。 - 具备GALS设计经验，熟悉跨时钟域处理方法（CDC）及相关EDA工具（如Mentor CDC Compiler、Synopsys SpyGlass）。 - 熟练使用Python编写自动化脚本，能高效完成数据解析、流程自动化、报告生成等工程任务。 加分项： - 有Arteris FlexNoC或同类商用NoC IP的实际使用经验，了解其配置流程与集成方法。 - 了解SystemC / TLM建模，能够进行事务级性能仿真与架构探索。 - 熟练使用Claude Code、GitHub Copilot、CodeX等AI辅助编程工具，具备将AI工具融入日常设计开发工作流的实践经验。

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