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Open nowPosted 72 days ago

NOC设计工程师

li/referral788 open roles

Where
Beijing, Chinese Mainland
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Your applicationOpen nowNOC设计工程师li/referral · Beijing, Chinese Mainland

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  3. 25 readersRecruiter, hiring manager, skeptic. Round after round.

  4. CV RocketApplied on li/referral's own form.

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The clock on this job

Early applications get read.

12.3% of postings close within 7 days. Measured by our own scanner across the market. li/referral postings stay open a median of 1 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.5%3 days
  3. 12.3%7 days
  4. 19.3%14 days
  5. 35.6%30 days
  6. 57.8%60 days
This job: posted 72 days ago

li/referral median: 1 days open

The posting

岗位职责 1. NoC 架构定义与探索：针对云端大模型推理的数据流特征（如 Transformer 算子的 Broadcast/Multicast 需求），主导自研 NoC 的拓扑结构（Mesh, Ring, Torus, Crossbar 等）、路由算法（Routing）、流量控制（Flow Control）及死锁避免（Deadlock-free）机制的设计与选型。 2. 微架构设计与 RTL 实现：负责 NoC 核心组件（Router, Network Interface, Switch, Arbiter 等）的微架构定义与 RTL 代码编写，确保极高的数据吞吐率与极低的传输延迟。 3. 系统级性能调优：建立 NoC 性能评估模型（C++/SystemC/Python），分析端到端延迟、带宽利用率及拥塞（Congestion）情况；设计高效的 QoS（服务质量）仲裁策略，保障高优先级任务（如 CPU 控制流）与海量张量数据流的完美协同。 4. 物理感知设计（Physical-aware Design）：与后端物理设计（PR）团队紧密合作，在架构初期充分考虑先进制程（5nm/3nm）下的绕线拥塞、长线延迟（Wire Delay）与时序收敛（Timing Closure）问题，实现物理友好的 NoC 设计。 5. 前沿互联技术预研：参与下一代多片级联（Multi-die/Chiplet）互联架构的预研，支持 D2D（Die-to-Die, 如 UCIe）高速接口的 NoC 扩展。

任职要求 1. 教育背景：微电子、计算机、电子工程等相关专业，硕士及以上学历，5 年以上大规模数字 IC 设计或架构经验。 2. 核心经验：具备至少一款大型高性能 SoC（AI 芯片、GPU、CPU、DPU 或网络交换芯片）的 NoC 设计或深度定制经验；有成功流片及硅后点亮（Bring-up）经验者优先。 3. 协议与理论扎实：深入理解片上网络理论（拓扑、路由、流控、死锁避免）； 4. 代码与工具能力：精通 Verilog/SystemVerilog，具备扎实的 RTL 编码功底；熟悉主流 EDA 综合与时序分析工具；有使用商业 NoC 生成工具（如 Arteris FlexNoC, ARM CoreLink）并进行过深度二次开发者亦可。 5. 软硬协同思维：了解深度学习算法（CNN, Transformer）的基本数据流特征，能够从编译器/软件调度的角度思考 NoC 的数据搬运效率。 6. 综合素质：具备极强的系统级 Debug 能力，能够清晰界定复杂系统中的性能瓶颈；具备良好的跨部门沟通能力（与架构、验证、后端、软件团队协同）。

加分项 1. 具备从 0 到 1 纯自研 NoC（非依赖第三方 IP）成功量产经验者优先。 2. 熟悉 HBM 内存子系统架构及访存调度策略者优先。 3. 具备 C++/SystemC 周期级（Cycle-accurate）性能建模经验者优先。

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