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Open nowPosted 45 days ago

前端RTL设计专家-RTL设计二组

li/referral787 open roles

Where
Beijing, Chinese Mainland
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Your applicationOpen now前端RTL设计专家-RTL设计二组li/referral · Beijing, Chinese Mainland

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The clock on this job

Early applications get read.

11.5% of postings close within 7 days. Measured by our own scanner across the market. li/referral postings stay open a median of 1 days.

Share of postings closed within
  1. 2.0%1 day
  2. 4.3%3 days
  3. 11.5%7 days
  4. 18.1%14 days
  5. 35.6%30 days
  6. 44.6%60 days
This job: posted 45 days ago

li/referral median: 1 days open

The posting

岗位职责 1. 负责 AI 算力芯片关键模块的前端设计与交付，包括需求分析、微架构设计、RTL 编码、模块集成与问题定位。 2. 对 RTL 代码质量负责，建立并推动设计规范落地，包括但不限于代码风格、lint、CDC/RDC、可综合性、可维护性与可复用性。 3. 参与芯片/子系统级设计规划，包括设计层级划分、模块边界定义、时钟/复位方案、跨时钟域策略、接口协议设计及集成方案。 4. 根据整体架构需求，对具体功能模块进行微架构设计，完成数据通路（datapath）与控制通路（control path）的定义、性能权衡与实现落地。 5. 负责关键模块的接口定义及时序/吞吐/面积/功耗等设计权衡，推动架构方案在实现层面的闭环。 6. 与验证、后端、DFT、系统软件及架构团队紧密协作，支持从规格定义、设计实现到验证收敛、综合实现和问题 debug 的完整研发流程。 7. 参与设计评审，识别并规避前端设计风险，持续优化设计方法论、开发流程和工程效率。 8. 支持芯片 bring-up 及量产阶段的问题分析，协助定位设计相关 root cause。

任职要求 1. 微电子、电子工程、计算机体系结构、通信等相关专业硕士及以上学历。 2. 具备扎实的数字电路基础，熟悉同步设计方法学，理解流水线、仲裁、缓存/存储、总线协议、时钟/复位、电源管理等基本设计问题。 3. 熟练掌握 Verilog/SystemVerilog，具备良好的 RTL 编码习惯和工程化能力，能够独立完成中大型模块设计。 4. 熟悉前端设计质量控制流程，具备 lint、CDC、RDC 等问题分析与收敛经验 5. 有较强的微架构设计能力，能够基于规格完成模块分解、接口定义、状态机设计、数据流/控制流设计以及性能瓶颈分析。 6. 熟悉常见片上接口协议和设计模式，如 AXI/AHB/APB、ready/valid、FIFO、credit-based flow control 等。 7. 熟悉时钟架构与复位设计方法，能够合理规划时钟域、复位域及跨域同步方案。 8. 具备良好的问题分析和 debug 能力，能够跨团队推动设计问题闭环。 9. 有5年及以上数字前端设计经验；有高性能计算、AI 加速器、GPU/NPU、NoC、DMA、片上缓存、存储子系统等相关经验者优先。 加分项 1. 有 AI 加速器、矩阵计算单元、向量处理单元、张量计算数据通路等相关设计经验。 2. 有芯片级/子系统级集成经验，主导过设计层级规划、接口规范制定或编码规范建设。 3. 熟悉低功耗设计方法，如 clock gating、power domain 配合、UPF/CPF 协同意识。 4. 有与综合、STA、物理实现协同优化经验，理解前后端协同对 RTL 设计的SDC约束。 5. 有带团队、做设计评审、培养初中级工程师经验者优先。 综合素质 1. 对设计质量有较高标准，能从规范、方法和实现细节上把控风险。 2. 具备系统性思维，既能从芯片/子系统层面看问题，也能深入具体模块实现。 3. 沟通协作能力强，能够推动架构、验证、后端等多团队达成一致并高效执行。 4. 对高性能、高带宽、低功耗设计有持续钻研兴趣。

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