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Open nowPosted 63 days ago

2027校招-算子开发工程师（上海/北京/成都）

smartlogictech/xiaozhao44 open roles

Where
Shanghai, Chinese Mainland
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Your applicationOpen now2027校招-算子开发工程师（上海/北京/成都）smartlogictech/xiaozhao · Shanghai, Chinese Mainland

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11.5% of postings close within 7 days. Measured by our own scanner across the market.

Share of postings closed within
  1. 2.0%1 day
  2. 4.3%3 days
  3. 11.5%7 days
  4. 18.1%14 days
  5. 35.6%30 days
  6. 44.6%60 days
This job: posted 63 days ago

The posting

"岗位职责 - 负责公司自研 AI 加速芯片上的 算子库设计与实现，覆盖训练与推理核心算子（如 GEMM/Conv/Attention/LayerNorm/Softmax/Reduce/Scatter-Gather 等）。 - 基于芯片计算单元、片上存储（SRAM/Cache）、HBM 带宽、NoC 拓扑、DMA/异步拷贝能力，进行 算子性能建模与瓶颈分析（roofline、访存/计算比、流水并行），制定优化策略。 - 设计并落地 kernel 调度与 tiling 策略：多级分块、数据布局（layout/packing）、向量化/张量化、双缓冲/多缓冲、算子融合（fusion）等。 - 建设算子库工程化体系：算子接口规范、版本管理、性能回归、单测/对齐验证、精度与数值稳定性、跨平台兼容 - 参与端到端模型性能优化：对接 PyTorch/TensorFlow/ONNX Runtime 等前端（或公司自研框架），完成算子覆盖、性能调优和线上问题定位（profiling/trace）。"

"（优秀应届可放宽）。 - 计算机/电子/自动化/数学等相关专业； - 熟悉深度学习常见算子与数值实现（GEMM/Conv/Attention/Norm/Reduce），理解训练/推理的差异（激活、梯度、混合精度、量化）。 - 扎实的 C/C++ 能力，良好的工程习惯；能熟练使用性能分析工具（profiling、trace、perf、火焰图或自研工具）。 - 熟悉至少一种加速器编程模型或并行体系（CUDA/OpenCL/ROCm/Metal/TVM/Triton/oneDNN/CUTLASS 等）并能迁移到自研 ISA/Runtime。 - 具备系统级性能意识：理解存储层次、带宽/延迟、cache/预取、NUMA、DMA、并行同步等，对算子优化有方法论。 加分项 - 有自研芯片/FPGA/NPU/GPU 上 kernel 开发经验；熟悉片上 SRAM、NoC、DMA、多队列/中断驱动等硬件特性。 - 熟悉编译器基础（LLVM/MLIR/TVM/Glow/XLA），做过算子自动调参（auto-tuning）、算子融合、IR pattern 优化。 - 有大模型推理优化经验：Attention/KV-cache、FlashAttention 类算法、量化（INT8/FP8/FP4）、MoE、通信算子（AllReduce/AllGather）。 - 熟悉算子库生态：cuDNN/cuBLAS/oneDNN/MKLDNN、MIOpen、Triton、CUTLASS、OpenAI Triton 或 TVM schedule。 - 有数值分析能力：误差传播、稳定性、低精度计算技巧（loss scaling、stochastic rounding）。 你将获得 - 深度参与从 硬件能力 → 编程模型 → 编译/运行时 → 算子库 → 端到端模型 的全栈优化闭环。 - 与架构/编译器/框架团队协作，直接影响芯片在大模型训练与推理场景的性能与易用性。"

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