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端侧NPU性能建模工程师 - PICO

ByteDance19,033 open roles

Where
Beijing, Chinese Mainland
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Your applicationOpen now端侧NPU性能建模工程师 - PICOByteDance · Beijing, Chinese Mainland
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12.8% of postings close within 7 days. Measured by our own scanner across the market. ByteDance postings stay open a median of 7 days.

Share of postings closed within
  1. 2.2%1 day
  2. 4.5%3 days
  3. 12.8%7 days
  4. 20.6%14 days
  5. 35.6%30 days
  6. 58.4%60 days
This job: posted 2 hours ago

ByteDance median: 7 days open

The posting

团队介绍:作为一家拥有自主创新和研发创造能力的科技品牌,PICO致力于成为领先的世界级XR平台,成就开发者与创作者,共同为全球消费者创造更美好的生活体验。我们开创性地将虚拟现实扩展到了多个领域,为运动、视频、娱乐等消费级场景带来了全新体验;并广泛应用在教育、医疗和企业培训等商用场景,给全球企业级用户提供了多元化的VR解决方案。

1、负责端侧NPU性能与功耗模型的开发和维护,覆盖核心计算单元、片上互联、多级存储架构(SRAM/缓存/DRAM)及DMA数据搬运机制; 2、构建端侧NPU性能与功耗评估体系,搭建评测流程与工具,支持不同架构配置下的快速评估与对比; 3、负责前沿端侧模型(包括经典及轻量级CNN、Transformer等架构)在NPU上的性能评估,分析计算强度、内存占用、访存带宽需求及算子级执行延迟; 4、与算法团队协作,结合硬件特性探索算子切分与分块、向量化及调度策略,评估算子融合与内存复用方案对时延、内存开销与功耗的影响; 5、基于仿真数据开展端到端性能瓶颈分析,向架构团队输出评估结论与优化建议,支撑NPU架构规格制定。

1、本科及以上学历,计算机科学、电子工程、微电子等相关专业,或具备同等实践经验; 2、具备3年及以上芯片体系结构建模或电子系统级建模的工业界项目经验; 3、熟练掌握C/C++及SystemC编程,具备良好的软件工程能力与底层调试能力; 4、理解计算机体系结构核心概念,包括内存子系统、缓存层次结构、DMA控制器、分块优化、向量化、脉动阵列及片上互联; 5、有机器学习专用加速芯片分析型性能与功耗模型构建经验者优先; 6、熟悉端侧推理中的定点量化、稀疏化策略,以及PyTorch、ONNX、TFLite等深度学习框架的算子图结构者优先。

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